e-mail: firstname.lastname@example.org Fourth International Conference I.TECH 2006 IMAGE SENSORS IN SECURITY AND MEDICAL APPLICATIONS Evgeny Artyomov, Alexander Fish, Orly Yadid-Pecht Abstract: This paper briefly reviews CMOS image sensor technology and its utilization in security and medical applications. The role and future trends of image sensors in each of the applications are discussed. To provide the reader deeper understanding of the technology aspects the paper concentrates on the selected applications such as surveillance, biometrics, capsule endoscopy and artificial retina. The reasons for concentrating on these applications are due to their importance in our daily life and because they present leading-edge applications for imaging systems research and development. In addition, review of image sensors implementation in these applications allows the reader to investigate image sensor technology from the technical and from other views as well.
1. Introduction Fast development of low-power miniature CMOS image sensors triggers their penetration to various fields of our daily life. Today we are commonly used to meet them in digital still and video cameras, cellular phones, web and security cameras, toys, vehicles, factory inspection systems, medical equipment and many other applications (see Figure 1). The advantages of current state-of-the-art CMOS imagers over conventional CCD sensors are the possibility in integration of all functions required for timing, exposure control, color processing, image enhancement, image compression and analog-to-digital (ADC) conversion on the same chip. In addition, CMOS imagers offer significant advantages in terms of low power, low voltage, flexibility, cost and miniaturization. These features make them very suitable especially for security and medical applications. This paper presents a review of image sensors utilization in part of the security and the medical applications.
Figure 1. Image sensors applications During the last few years imaging systems for security applications have been significantly revolutionising. Large, high cost and inefficient cameras mostly used for specific military and government applications have been replaced with compact, low-cost, low-power smart camera systems, becoming available not only for military and government, but for wide spreading in civilian applications. In this paper we will concentrate on two major categories: (a) surveillance systems – usually used for observation, anomaly detection and alarming, employing one or multiple cameras, (b) biometrics systems – used for access control and person identification. Each of the Information Technologies in Biomedicine presented categories requires sensors having different specifications: for example, while low-power and compactness are the most important features for some surveillance systems, robustness and high image quality are the most important requirement in biometric systems.
Medical applications also benefit from the fast image sensors technology development. Introduction of miniature, ultra-low power CMOS image sensors have opened new perspectives to minimally-invasive medical devices, like wireless capsules for gastrointestinal tract observation . Here we will review two very important medical applications:
(a) artificial retina – used as an artificial replacement or aid to the damaged human vision system, (b) wirelss capsule endoscopy – used in minimally invasive gastrointestinal tract diagnostics.
The remainder of the paper is organized as follows: Section II briefly presents CMOS image sensor technology with reference to "smart" CMOS image sensor architecture. The role of image sensors in security applications is described in Section III. Section IV reviews medical applications employing state-of-the-art CMOS imagers.
Section V concludes the paper.
2. CMOS Image Sensor Technology in a Glance The continuous advances in CMOS technology for processors and DRAMs have made CMOS sensor arrays a viable alternative to the popular charge-coupled devices (CCD) sensor technology. Standard CMOS mixed-signal technology allows the manufacture of monolithically integrated imaging devices: all the functions for timing, exposure control and ADC can be implemented on one piece of silicon, enabling the production of the so-called “camera-on-a-chip” . Figure 2 is a diagram of a typical digital camera system, showing the difference between the building blocks of commonly used CCD cameras and the CMOS camera-on-a-chip . The traditional imaging pipeline functions—such as color processing, image enhancement and image compression—can also be integrated into the camera. This enables quick processing and exchanging of images. The unique features of CMOS digital cameras allow many new applications, including network teleconferencing, videophones, guidance and navigation, automotive imaging systems, robotic and machine vision and of course, security and bio-medical image systems.
Figure 2. Block diagram of a typical digital camera system.
Most digital cameras still use CCDs to implement the image sensor. State-of-the-art CCD imagers are based on a mature technology and present excellent performance and image quality. They are still unsurpassed for high sensitivity and long exposure time, thanks to extremely low noise, high quantum efficiency and very high fill factors. Unfortunately, CCDs need specialized clock drivers that must provide clocking signals with relatively Fourth International Conference I.TECH 2006 large amplitudes (up to 10 V) and well-defined shapes. Multiple supply and bias voltages at non-standard values (up to 15 V) are often necessary, resulting in very complex systems.
Figure 3 is a block diagram of a widely used interline transfer CCD image sensor. In such sensors, incident photons are converted to charge, which is accumulated by the photodetectors during exposure time. In the subsequent readout time, the accumulated charge is sequentially transferred into the vertical and horizontal CCDs and then shifted to the chip-level output amplifier. However, the sequential readout of pixel charge limits the readout speed. Furthermore, CCDs are high-capacitance devices and during readout, all the capacitors are switched at the same time with high voltages; as a result, CCD image sensors usually consume a great deal of power. CCDs also cannot easily be integrated with CMOS circuits due to additional fabrication complexity and increased cost. Because it is very difficult to integrate all camera functions onto a single CCD chip, multiple chips must be used. A regular digital camera based on CCD image sensors is therefore burdened with high power consumption, large size and a relatively complex design; consequently, it is not well suited for portable imaging applications.
photodetector light Horizontal CCD Output (analog shift register) amplifier Figure 3. Block diagram of a typical interline transfer CCD image sensor.
Unlike CCD image sensors, CMOS imagers use digital memory style readout, using row decoders and column amplifiers. This readout overcomes many of the problems found with CCD image sensors: readout can be very fast, it can consume very little power, and random access of pixel values is possible so that selective readout of windows of interest is allowed. The power consumption of the overall system can be reduced because many of the supporting external electronic components required by a CCD sensor can be fabricated directly inside a CMOS sensor. Low power consumption helps to reduce the temperature (or the temperature gradient) of both the sensor and the camera head, leading to improved performance.
An additional advantage of CMOS imagers is that analog signal and digital processing can be integrated onto the same substrate, allowing fabrication of so called "smart" image sensors. Many "smart" image sensors have already been demonstrated in the literature. They performed functions of real time object tracking -, motion detection -, image compression -, widening the dynamic range of the sensor - and others. These functions are usually performed by digital or nonlinear analog circuits and can be implemented inside the pixels and in the periphery of the array. Offloading signal processing functions makes more memory and DSP processing time available for higher-level tasks, such as image segmentation or tasks unrelated to imaging.
Vertical CCD (analog shift register) Information Technologies in Biomedicine CMOS pixels can be divided into two main groups, passive pixel sensors (PPS and active pixel sensors (APS).
Each individual pixel of a PPS array has only a photosensing element (usually a photodiode) and a switching MOSFET transistor. The signal is detected either by an output amplifier implemented in each column or by a single output for the entire imaging device. These conventional MOS-array sensors operate like an analog DRAM, offering the advantage of random access to the individual pixels. They suffer from relatively poor noise performance and reduced sensitivity compared to state-of-the-art CCD sensors. APS arrays are relatively novel image sensors that have amplifiers implemented in every pixel; this significantly improves the noise parameter.
Figure 4 shows the general architecture of the "smart" CMOS APS based image sensor. The core of this architecture is a camera-on-a-chip, consisting of a pixel array, a Y-addressing circuitry with a row driver, an Xaddressing circuitry with a column driver, an analog front end (AFE), an analog-to-digital converter (ADC), a digital timing and control block, a bandgap reference and a clock generator. Optional analog and digital processing blocks "upgrade" the camera-on-a-chip core to a "smart" imager, and they are used to perform additional functions, that can vary from design to design, depending on the application and system requirements.
Figure 4. General architecture of the "smart" CMOS APS based image sensor.
The basic imager operation, depends on the chosen photodetector and pixel types, readout mode, Y-addressing and X-addressing circuitries, ADC type and of course, the analog and/or digital image processing. A brief description of the main imager building blocks is presented herein.
A. APS Pixel Array – the imager pixel array consists of N by M active pixels, while the most popular is the basic photodiode APS pixel, employing a photodiode and a readout circuit of three transistors. Generally, many types of photodetectors and pixels can be found in the literature. This includes a p-i-n photodiode, photogate and pinned photodiode based pixels, operating either in rolling shutter or in global shutter (snapshot) readout modes. The difference between these modes is that in the rolling shutter approach, the start and end of the light collection for each row is slightly delayed from the previous row, leading to image distortion when there is relative motion Fourth International Conference I.TECH 2006 between the imager and the scene. On the other hand, the global shutter technique uses a memory element inside each pixel and provides capabilities similar to a mechanical shutter: it allows simultaneous integration of the entire pixel array and then stops the exposure while the image data is read out. A detailed description of both rolling shutter and global shutter pixels can be found in .
Note, although most of today's "cameras-on-a-chip utilize" very simple pixels, many "smart" imagers employ more complicated pixels. Some of them perform analog image processing tasks at the pixel level. Very good examples for these imagers are neuromorphic sensors, where each pixel consists of a photo detector and local circuitry, performing spatio-temporal computations on the analog brightness signal. Another example is an imager, where the A/D conversion is performed in the pixel level.
B. Scanning Circuitry – Unlike CCD image sensors, CMOS imagers use digital memory style readout, usually employing Y-Addressing and X-Addressing to control the readout of output signals through the analog amplifiers and allow access to the required pixel. The array of pixels is accessed in a row-wise fashion using the YAddressing circuitry. All pixels in the row are read out into column analog readout circuits in parallel and then are sequentially read out using the X-Addressing circuitry (see Figure 4).
C. Analog Front End (AFE) - all pixels in a selected row are processed simultaneously and sampled onto sampleand-hold (S/H) circuits at the bottom of their respective rows. Due to this column parallel process, for an array having M columns, the AFE circuitry usually consists of 2*M S/H circuits, M size analog multiplexer, controlled by the X-Addressing circuitry, and one or M amplifiers to perform correlated double sampler (CDS). The CDS improves the signal-to-noise ratio (SNR) by eliminating the fixed pattern noise (FPN). A programmable- (or variable-) gain amplifier (PGA or VGA) follows the CDS to amplify the signal and better utilize the full dynamic range of the A/D converter (ADC).The number of amplifiers, required to perform the CDS functionality depends on the chosen CDS architecture and is equal to 2*N in case the subtraction is done separately for each column.
The choice of an AFE configuration depends on many factors, including: the type of sensor being used, dynamic range, resolution, speed, noise, and power requirements. The considerations regarding making appropriate AFE choices for imaging applications can be found in .
D. Analog-to-digital conversion (ADC) – ADC is the inherent part of state-of-the-art "smart" image sensors. There are three general approaches to implementing sensor array ADC:
1. Pixel-level ADC, where every pixel has its own converter -. This approach allows parallel operation of all ADCs in the APS array, so a very low speed ADC is suitable. Using one ADC per pixel has additional advantages, such as higher SNR and simpler design.
2. Column-level ADC, where an array of ADCs is placed at the bottom of the APS array and each ADC is dedicated to one or more columns of the APS array -. All these ADCs are operated in parallel, so a low-tomedium-speed ADC design can be used, depending on the sensor array size. The disadvantages of this approach are the necessity of fitting each ADC within the pixel pitch (i.e., the column width) and the possible problems of mismatch among the converters at different columns.
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