Figure 4 The X-COM and Y-COM update circuit implementation Information Technologies in Biomedicine 3.3 Current Mode Winner-take-all (WTA) circuit As mentioned, the X-COM and Y-COM update circuits utilize current mode WTA circuit. The implementation of the WTA circuit (see Figure 5) is very similar to the implementation of the LTA circuit, presented in sub-section 3.1 and detailed description of its operation can be found in . Similarly to the LTA, the WTA circuit employs inhibitory and local excitatory feedbacks based on input currents average computation, enhancing precision and speed performance of the circuit. Local excitatory feedback provides a hysteretic mechanism that prevents the selection of other potential winners unless they are stronger than the selected one by a set hysteretic current. The WTA circuit can be useful for integration with circuits operating in the strong inversion region and supplying input currents of 3A-50A, as well as for subthreshold applications with inputs of 0nA-50nA. It achieves very high speed (32nsec for high currents of 3A-50A (measured) and 34nsec for subthreshold currents – (simulated)) in case when a very small difference between two input currents is applied (30nA for high currents and 1.8nA for subthreshold applications). These circuit performances are the direct result from very strong feedbacks applied in the circuit. The circuit ability to cope with wide range of input currents is very important for the COM update circuit implementation since the inputs to this circuit can have very wide range.
Figure 5. Cells 1 and k (out of n) of the WTA circuit 3.4 Y-addressing and X-Addressing circuitry implementation Generally, the Y-Addressing and X-Addressing circuitry can be implemented using digital decoders. However, using shift registers for read out control reduces power dissipation and the number of global buses. In addition, windows of interest can be easily defined using shift-register. As previously mentioned, 2N shift registers are required to define N different windows. The architecture of shift register, used in the discussed tracking sensor (see Figure 6), is based on the conventional simple shift register structure and utilizes low-power D-Flip-Flops (DFFs), described in details in .
Fourth International Conference I.TECH 2006 This register allows shifting of the vector of bits right or left – very important function in windows definition. The power dissipation of the shift register can be reduced by examining the nature of the inputs to the register. When the register is used for signal readout control, its input vector consists of a single '1' and of (N-1) digital zeros ('0'), assuming an N size register. Thus, in steady state, only one (out of N) DFF has '1' in its output. For the case, when the register is used for window definition, its input vector consists of K high digital bits and (N-K) low digital bits, assuming an N size register defines K*K size window. Usually, K<
Sl' Sl' Sl' Sl Sl Sl Sr' Sr' Sr' Q D Q D Q D Sr Sr clk clk clk Sr clk Figure 6 Architecture of the conventional shift-right and shift-left register Figure 7. DFF, optimized for an input vector consisting of a large number of zeros To check the suitability of the mentioned DFF circuit for the proposed tracking system, it has been designed and implemented in 0.18m technology to compare the FF design with a set of representative flip-flops, commonly used for high performance design. In addition, the low leakage shift register is compared to the register, based on conventional FFs. Simulation results show up-to 10% power reduction in case of 10KHZ operation and up-to 60% Information Technologies in Biomedicine reduction in case of 5 pixels size window definition at 30Hz frequency. More detailed description of the FF and SR performances can be found in .
4. Discussion In this section we present the expected performance of the proposed tracking imager and briefly discuss advantages and limitations of the current architecture. Table 2 summarizes the expected characteristics of the proposed system. The sensor will be fabricated in a standard 0.18µm CMOS technology and will be operated using 1.8V supply voltage. The pixel size is expected to be 7 x 7µm and to achieve fill factor of at least 60%.
At this stage the test chip will include a relatively small array of 64 x 64. The reason for the small array is failure probability reduction and limited budget. On the other hand, this array size still allows showing the proof of concept. At the first fabrication phase the system will able to track up to 3 salient targets of interest at 30 frames per second. In future designs we are working to increase the number of the tracked targets and to improve real time operation, allowing tracking at up to 100 frames per second. As mentioned, the proposed imager employs spatial filtering version of the spotlight models of attention, where what falls outside the attentional spotlight is assumed not to be processed. The drawback of this method is that during the tracking mode the sensor filters all information outside windows of interest, including potential targets that appear in the FOV during the tracking. In our future implementations we plan to upgrade the tracking sensor with the spotlight attention model, where the spotlight serves to concentrate attentional resources to a particular region in space, thus enhancing processing at that location and almost eliminating processing of the unattended regions (but still checking theses regions). An additional limitation is that the proposed system does not utilize Correlated Double Sampling (CDS) circuit to reduce Fixed Pattern Noise (FPN). CDS implementation in such kind of tracker is not trivial and thus it will be implemented only in the next version of the system to reduce failure probability at this stage. Finally, the system is expected to achieve very low-power dissipation of less than 2mW. The next generation of this tracking system will achieve power dissipation of less than 1mW.
Parameter Expected value Technology 0.18µm standard CMOS technology Array size 64 x Voltage supply 1.8V Pixel Size 7 x 7 µm Fill Factor > 60% No. of tracked targets Real time operation 60 frames/second Sensor read out method Global Shutter Utilized Attention model Spatial Filtering Bad Pixel Elimination Yes FPN Reduction No Power Dissipation < 2mW Table 2: The expected characteristics of the tracking system.
Fourth International Conference I.TECH 2006 5. Conclusions Implementation of low-power tracking CMOS image sensor based on biological models of attention was presented. Imager architecture and principle of operation were discussed, as well designs of the most important circuits, like Winner-Take-All, Looser-Takes-All, COM update and X/Y-Addressing circuits, utilized by the tracking system were shown. A brief description of the spatial and object-based models of attention was also presented.
The expected system performance was discussed, showing advantages and drawbacks of the proposed sensor.
The presented imager allows tracking of up to N salient targets in the field of view. The imager architecture is optimized to achieve low-power dissipation both in acquisition and tracking modes of operation. Further research includes improvement of the current sensor architecture and its realization in an advanced CMOS technology.
Acknowledgements We would like to thank the Israeli Ministry of Science and Technology for funding this project.
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Authors' Information Alexander Fish – The VLSI Systems Center, Ben-Gurion University, Beer Sheva, Israel;
e-mail: firstname.lastname@example.org Liby Sudakov-Boreysha – The VLSI Systems Center, Ben-Gurion University, Beer Sheva, Israel;
e-mail: email@example.com Orly Yadid-Pecht – The VLSI Systems Center, Ben-Gurion University, Beer Sheva, Israel, and Dept. of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;
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