Information Technologies in Biomedicine Figure 2 shows the architecture of the proposed tracking sensor. The sensor includes (a) A Pixel array with a two dimensional resistive network, (b) Y-Addressing and X-Addressing circuitry consisting of N digital registers for target windows definition and for image readout control, (c) an analog front end (AFE) for image readout, (d) A current Looser-take-all (LTA) circuit for target detection during the acquisition mode, (e) two analog 1-D center of mass (COM) computation circuits for X and Y COM coordinates update (each consists of 1-D analog current mode Winner-take-all (WTA) circuit), (f) Analog memory for temporal storage of loser values of all rows during the acquisition mode and digital memory for targets coordinates storage, (g) acquisition mode control and target mode control blocks.
In the acquisition mode the sensor finds the N most salient targets in the FOV and calculates their centroid coordinates. This is achieved in the following way: all neighboring pixels are connected by resistors (implemented by transistors), creating the resistive network. The pixel voltage becomes smaller if it is more exposed, and the local minimum of the voltage distribution can be regarded as the centroid of the target, corresponding to the exposed area. This minimum is found using an analog looser-take-all circuit (LTA). At the first stage of the acquisition mode, all pixels of the whole image are activated. The global minimum, corresponding to the brightest target is located using a one dimensional LTA circuit. To achieve this purpose, the whole image is scanned row by row (using one of the digital shift registers in the Y-addressing circuitry), finding the local minimum in each row.
Then, the row local minima are input to the same LTA circuit again and the global minimum is computed. A more detailed description of this concept can be found in , where the two dimensional WTA computation was performed using two 1-D WTA circuits. Once the first brightest target is found, the system defines a small size programmable window, with the center located at the target centroid coordinates. The size of this window is predefined by the user before the acquisition mode starts and depends on the target size. While finding the second bright target in the FOV, all pixels of the first window, consisting of the brightest target found during the first search, are deactivated. This way, the bright pixels of the first target do not influence the result of the second search. The remains N-1 targets are found in the same way. As a result, at the end of the acquisition mode all centroid coordinates of the N most salient targets in the FOV are stored in the memory and N small windows around these coordinates are defined. The window definition is performed using two digital shift registers. Thus, 2N shift registers are required to define N different windows. The acquisition mode control block is responsible for defining and positioning these active windows. Note, that the acquisition mode is very inefficient in terms of power dissipation because the whole sensor array is activated and the LTA operation and windows definition are power inefficient operations. On the other hand, the acquisition is a very rare operation and its time can be neglected in comparison with the tracking period.
Once the sensor has acquired N salient targets, the tracking mode is initiated. The predefined windows serve as a spotlight in biological systems, such that only the regions inside the windows are processed. Opposite to biological systems, these "spotlights" attend only to the regions predefined in the acquisition mode. Thus, even if new more salient objects appear during the tracking, the attention to the chosen regions is not influenced.
Because the sensor is in the tracking mode most of the time, it is very important to achieve very low-power dissipation in this mode. In the proposed system this is achieved in the following ways:
1. Only pixels of active windows and the circuitry responsible for proper centroid detection and pixels readout are active. The remaining circuits (including most pixels of the array) are disconnected from the power supply.
2. All shift registers in Y-addressing and X-addressing circuitries are optimized for low frequencies operation by leakage currents reduction.
3. During the tracking mode the sensor doesn't calculate new centroid coordinates. A simple analog circuit (COM update block in Figure 2) checks if the new centroid location differs from the centroid location of the previous frame. In the case that no difference was found, the circuit does not need to perform any action, significantly reducing system power dissipation. This principle suits the general idea of "no movement – no action". If the target changes its position, the "shift left" or "shift right" (both for x and y) signals are produced Fourth International Conference I.TECH 2006 by the COM update blocks. These signals are input to the tracking mode control block and the appropriate shift register performs movement to the right direction, correcting the location of the window.
4. Each active window definition is performed using two shift registers. This windows definition method allows switching from one target of interest to another without any need in accessing the memory and loading the new target coordinates. This way the switching time between different objects does not depend on the distance between the targets and sensor power dissipation is reduced.
3. Circuits Description In this Section we present some of the most important circuits, utilized by the sensor. This includes current mode LTA circuit, current mode WTA circuit, X-COM and Y-COM update circuits and ultra low-power shift registers. The pixel is implemented as a standard global-shutter active pixel sensor (APS)  with current mode readout instead of a conventional source follower amplifier inside the pixel. This current mode readout allows parallel read out and summarization of currents from all pixels in the active window at the same time. These summarized currents then are used for further processing by the X-COM and Y-COM update circuits, as described below.
In addition, a conventional video data readout is available.
3.1 Current Mode Loser-Take-All (LTA) circuit As previously mentioned, LTA circuit is responsible for targets detection and their COM computation during the acquisition mode. Since the COM computation is done in a serial manner and should be performed accurately, high speed and high precision LTA circuit is required. In addition, current mode LTA is required (pixels outputs are currents). Most of the previously presented LTA solutions are not suitable for the proposed sensor design. As a result, we use a LTA circuit that we have recently developed to achieve high speed and high precision .
Figure 3: Cells 1 and k (out of N) of the LTA circuit.
Figure 3 shows cells 1 and k (out of the N interacting cells) of the LTA circuit. Cell k receives a unidirectional input current, I, and produces an output voltage V. This output has a low digital value if the input current I is ink outk k identified as loser, and high, otherwise. The circuit applies two feedbacks to enhance the speed and precision:
the excitatory feedback I and inhibitory feedback I. The basic operation of the LTA is based on input k avgk currents average computation and comparison of the input current of each cell to that average. The local excitatory feedback works to increase the compared average value in each cell, allowing that cell to be a loser.
Oppositely, the inhibitory feedback works globally by reduction of the input currents average value and thus allowing inhibition of non-losing cells. A more detailed description of the circuit operation is provided below. The Information Technologies in Biomedicine LTA circuit operates as follows: the drains of M transistors of all N cells of the array are connected to the drains of M transistors by a single common wire with voltage Vcom. The circuit starts the competition by applying Rst='1' for a short period of time. This way the excitatory feedback Iin and the inhibitory feedback Iavg are k cancelled. Assuming that all N cells in the array are identical and Rst='1' is applied, Iavg = 0A and the current k I'avg, through M1, is equal to the average of all input currents of the array, neglecting small deviations in the k referenced input currents. I'avg is copied to M3 by the NMOS current mirror (M1 and M3 ) and is compared with k k k the input current Iin copied by the PMOS current mirror (M2 and M5 ). If Iin =I'avg then Vout =VDD/2, assuming k k k k k the same drivability factor K of M3 and M5 transistors.
k k An increase in input current Iin relatively to I'avg causes an increase in Vout due to the Early effect. This way, k k during the reset phase, input currents of all cells are compared to the average of all input currents of the array, producing a unique output Vout for every cell. The cell having the smallest input current value produces the k smallest Vout voltage. With the completion of the reset phase, i.e. Rst='0', the excitatory feedback I and the k k inhibitory feedback Iavg are produced. The Vout node inputs to the gate of M6 PMOS transistor, thus the cell k k k with the smaller Vx (smaller input current) produces a higher current I7 through M6 and M7. This current is k k k k copied by the NMOS current mirror (M7 and M8 ), creating the excitatory feedback I. On the other hand, I7 is k k k k copied by the NMOS current mirror (M7 and M9 ), resulting in inhibitory feedback Iavg. Ik is added to the k k k I'avg flowing through M3 and Iavg is subtracted from the average of all input current by connection Mk k k transistor to the COM node, decreasing the I'avg value. This way, every cell produces a new Voutk voltage value, according to the comparison between the input current Iin and a sum of a current produced by the excitatory k feedback I and a new value of current I'avg, that is now given by:
k N N N Iink Iavgk Iavgk k =1 k =1 k =I 'avg == Iavg N N (1) where Iavg is the average of all input currents of the array and N is the number of array cells. For the cell, having the smallest input current, the difference between Iin and a sum of I and I'avg grows, thus decreasing k k Vout value.
k The computation phase is finished after one cell only is identified as a loser, producing Vout =’0’. All other cells k are identified as winners with Vout =’1’. In this steady-state the excitatory and inhibitory feedbacks of the all k winner cells and I'avg are approximately equal to zero, while Iavg of the loser cell is approximately equal to the k sum of all input currents. This way the circuit states stable preventing the selection of other potential losers unless the next reset is applied and a new computation starts. A more detailed description on the circuit operation can be found in .
To examine the presented LTA circuit it was designed, simulated and fabricated in 0.35um, 3.3V, n-well, 4-metal, CMOS, TSMC technology process supported by MOSIS. Table 1 summarizes the main characteristics of the circuit. As can be seen, the circuit achieves both high precision and high speed.
Parameter Typical value Worst case value (if exists) Range of input currents 4 – 25 [A] -----Voltage supply 1.8V ------ Power Dissipation 58uW per cell 75 W per cell Delay 5nsec 95nsec Precision 0.1 A 0.5 A Occupied area (per cell) 26m*22m -----Table 1: The main characteristics of the designed circuit.
Fourth International Conference I.TECH 2006 3.2 X-COM and Y-COM update circuits As mentioned, during the tracking mode the sensor doesn't calculate the new centroid coordinates. Instead, very simple X-COM and Y-COM update circuits (see Figure 4) check if the new X or Y centroid locations (respectively) differ from the centroid locations of the previous frame. In the case that no difference was found, the sensor does not perform any action, significantly reducing system power dissipation. The X-COM and Y-COM circuits have the same implementation, consisting of (K+1) controlled resistors (implemented by transistors), (K+2) digital switches, controlled by window location and (K+2) size analog current mode WTA circuit for the array, having K columns/row, respectively. Each COM update circuit receives K unidirectional input currents from the sensor array. The input current I to the X-COM update circuit is the sum of all output pixel currents of the column K, ink while from the input current I to the Y-COM update circuit is the sum of all output pixel currents of the row K.
ink During the tracking mode (the COM update circuits are activated only in this mode), only pixels inside the windows of interest are activated. Therefore, in this mode, the input current to the COM circuit I represents the ink sum of all row/column K active window output currents, for the case where the row/column K falls into the window of interest. In case, where the row/column K falls out the window of interest, the value of I is zero. All input ink currents input to the resistive network, consisting of (K+1) controlled resistors (can either have a normal resistance R or very high resistance R ) and then routed to the WTA circuit by switches. Both switches and the high resistors are controlled by the windows of interest locations. For the active window, spread between column i and column (i+c), the resistors 1 to (i-1) and (i+2) to (K+1) have very high resistance R, while the resistors i to (i+1) high are set to have a normal resistance R. This way resistive network, consisting of R value resistors is created around the active window of interest. Only two switches (i-1) and (i+1) are set to be on, while the others are set to be off. As a result, the WTA circuit receive only two non-zero input currents, representing the X/Y COM coordinates of the target located inside the window of interest. In case these currents are equal (the WTA circuit does not succeed to find the winner), the COM coordinates are exactly in the center of the window and therefore window location update is not required. On the other hand, if (i-1) current is larger than (i+1), it means that the target has moved right relatively to its location in the previous frame and Shift Right output is activated. In case if (i-1) current is smaller than (i+1), the Shift Left output is activated.
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