, 1999, 41, . 5 Relaxation into Tunnel Induced Non-equilibrium States in Metal Oxide Semiconductor Structures A. Vercik, A. Faign Devices Physics-Microelectronics Laboratory, Faculty of Engineering, University of Buenos Aires, Paseo Coln 850, (1063) Buenos Aires, Argentina E-mail: avercik@fi.uba.ar The relaxation of a Metal Oxide Semiconductor structure from deep depletion towards a tunnel induced nonequilibrium stationary state is addressed in this work. A simple model was constructed, taking into account thermal generation, tunneling of both types of carriers and impact ionization. Experimental results obtained on p- and n-type Si substrates and oxides thinner than 6.5 nm are shown to be well fitted by the proposed model. A map describing the possible behavior patterns for a structure with given oxide thickness and effective generation velocity is presented.

The transients in an Metal Oxide Semiconductor (MOS) 1. Theory structure relaxing from deep depletion towards equilibrium were previously investigated in connection with the charac- The measured current in the external circuit after applying terization of the minority carriers generation mechanisms.

a reverse voltage step to an n-MOS diode is given by [5] It is assumed, for the methods to be applicable, that dQdep the transient ends in the thermal equilibrium state. The Jm = Jdisp + Jtp +Jtn = Jg + + Jtn, (1) presence of tunneling currents alters this behavior, affecting dt the transient to yield a steady state different from thermal where Jdisp is the displacements current due to changes in equilibrium [15].

the charge distribution within the semiconductor, and Jtp and Very thin oxide samples exhibit similar transients for both Jtn are the conduction currents which in this case correspond p- and n-type substrates. This symmetry breaks down for to tunneling currents for holes and electrons, respectively. Jg oxide thicknesses above 3.5 nm. Three qualitatively different is the minority carrier generation current into the inversion behavior patterns, depending of the oxide thickness, can be layer, and Qdep is the space charge in the depleted region.

identified through current transient curves for the n-type Charge conservation in integral form, applied to the substrate samples. From the analysis of the associated inversion layer, is expressed as follows:

currents, the three patterns correspond to i) p-type substrate samples and very thin oxide n-samples for which minority dQinv carriers seem to dominate the tunneling current, ii) interme= Jg - Jtp, (2) dt diate oxide thickness (36 nm) on n-substrates, for which the tunneling current is dominated by majority carriers but where Qinv is the inversion layer charge. Using the conserthe whole current is limited by the generation of minority vation of the electric displacement vector, the inversion layer carriers, and iii) thicker oxides on n-substrates, for which the charge takes the form impact ionization mechanism removes the limit imposed to the current by supplying minority carriers. ox Qinv = Vg - Vs - qNW, (3) The problem of modeling the relaxation of a MOS d structure from deep depletion into tunnel induced nonwhere Vg is the applied voltage, Vs is the semiconductor equilibrium states is addressed in this work.

potential, d is the oxide thickness, ox is the oxide dielectric An exact formulation of this problem requires the couppermittivity, q is the electron charge, N is the dopant ling Poisson equation, continuity equations for holes and concentration, and W is the depletion region width. Using electrons, and complete expressions for the pair generation the known dependence of W on Vs, the variation of Qinv with process, tunneling and impact ionization. An integral time in terms of variations of Vs results in treatment for the continuity equations, as used in this work, leads to a unique differential equation describing the dQinv ox s dVs = +, (4) evolution towards equilibrium.

dt d W(Vs) dt The model was tested by reproducing experimental results in the three regimes, and was used to analyze the where s is the semiconductor dielectric permittivity. Redependence of each type of behavior on the thickness and placing in eq. (2) we obtain the differential equation for Vs generation parameters.

A map for the relationship between oxide thickness and dVs Jg - Jtp =. (5) s thermal to obtain a given behavior pattern is given.

dt Cox + W Relaxation into Tunnel Induced Non-equilibrium States in Metal Oxide Semiconductor Structures The total generation current is written as W Vg - Jg = qni + Si 1-exp 2g 2kT + qSd (peq - ps), (6) s where ni is the intrinsic concentration, k is the Boltzmann constant, g is the bulk generation lifetime, Si is the value of the surface generation when the surface is inverted, and Sd is the generation velocity for the depleted surface, given by [6]:

N Sd = S0, (ps + 2ni) where S0 is a constant parameter, is the difference between the metal Fermi level and the minority carrier quasi Fermi Figure 1. Experimental (solid) and calculated (dotted) curves, for a p-type sample, 4.5 nm oxide thickness, with different voltage level, ps is the surface minority carrier concentration, which pulses. A is the gate area.

in terms of Vs is (Vg - Vs)2 ox 2 qN kT ps = - |Vs| -, (7) 2kT s d kT q where peq is the equilibrium minority carrier concentration s at the surface calculated from eq. (7) with Vs = Vseq, the equilibrium semiconductor voltage drop calculated in [4,7].

The number of pairs generated by impact in the space charge region for Vox > 1.7 V, approximately, [8] (Vox = Vg - Vs) is Jgi = WJtn, (8) where is the number of ionized pairs per unit of distance and Jtn is the majority carrier tunneling current [9].

The extraction of minority carriers by tunneling was modeled with the following expression:

ps Jtp = Ch 2 +Jg exp(-2k0d) exp(-hqVox), (9) Figure 2. Experimental (solid) and calculated (dotted) curves, for hN an n-type sample, 3.7 nm oxide thickness.

where Ch, h are numerical constants for the hole tunneling.

Eq. (9) keeps the exponential dependence of the current on the oxide voltage drop reported for the direct tunneling regime [9]. The prefactor in this expression represents the total supply of carriers with velocity normal to the barrier. It is composed by carriers in the inversion layer with the first term proportional to ps [10], and the carriers generated and driven to the surface, Jg.

2. Experimental Results Fitting The transient currents of a pulsed MOS diode into depletion can be classified, as was shown in a recent work [5], in three different behavior patterns, as follows.

a) Dominance of the current by minority carrier tunneling.

b) Tunneling of both type of carriers, with the current llimited by the generation of minority carriers.

c) Tunneling of both type of carriers without limitation Figure 3. Experimental (solid) and calculated (dotted) curves, for by the minority carrier generation which is enhanced by an n-type sample, 6.3 nm oxide thickness.


, 1999, 41, . 864 A. Vercik, A. Faign Case a) is observed in the p-type substrate capacitors transient (Fig. 2) due to the presence of a majority tunneling or in n-type with very thin insulators (up to about 3 nm). current without impactionization region II.

In n-samples with oxides between 3 and 6 nm, the impact The boundaries between these regions, can be determined ionization may occur but is insufficient for removing the as follows. The condition to be fulfilled by a diode to lay in generation limitation (case b). Case c) occurs for n-substrate region III is that the stationary oxide voltage drop must be greater that the threshold for impact ionization, to ensure samples with oxides thicker than about 6 nm.

that impact ionization will begin during the evolution to Fig. 1 to 3 show a family of experimental curves pertaining equilibrium. Thus, from eq. (10) with Vox = 1.7 V, the to each one of the described cases fitted with the model boundary between regions II and III is obtained. Diodes proposed above. Details of the experimental work are given with higher Sef f or thicker oxide will exhibit the typical thick in ref. [5].

structure like behavior pattern.

Structures will be in region I if the surface is not inverted 3. Discussion in the stationary state, so, the surface generation velocity will take a value between S0 and Si. Any tunneling In contrast to p-samples in which a unique kind of tran- current growth will be screened by the decreasing generation sient curve is measured, the behavior during the relaxation current. The minimum level of generation current before into tunnel induced non-equilibrium states in Metal Oxide the inversion (or the maximum generation current when Semiconductor structures with n-Si is determined by the the surface is inverted) is obtained by replacing in the bulk oxide thickness and minority carrier generation parameters. generation expression the depletion width value immediately The carrier generation can be characterized by an effective after the pulse, W0, given by velocity, Sef f, as the total generation current density Jg divided qni. In the stationary state, the generation current As 2VgCox W0 = 1 - - 1, (11) should equal the hole tunnel current, Jtp. Thus, for the steady Cox qNs Astate the effective generation velocity is and then, the generation in this case will be Jtp(Vox, d) Sef f =. (10) Wqni Jg = qni + qniSi. (12) 2g A map for the different behaviors can be constructed The initial oxide voltage in this situation is plotting this velocity versus the oxide thickness (Fig. 4).

This plot is divided into three regions. Structures laying qNWin region I will exhibit curves like those shown in Fig. 1 Vox = Vg -. (13) 2s for 3 and 8 V. No transient other than the decay of the surface generation velocity from its depleted value, S0, to The prefactor in expression (9) for Jtp, i. e., the incident a stationary value, greater or equal to Si can be measured current, will be governed by Jg provided that the minority on these diodes. Structures with parameters in region III, carrier concentration at the surface is too small. Replacing are those for which impact ionization spontaneously begins, (9), (12) and (13) in eq. (10), the resulting Sef f vs. d curve enhancing generation of minority carriers (Fig. 3). Diodes represents the lowest boundary between regions I and II, i. e., between these two regions will show an increasing current diodes with smaller Sef f or d will exhibit a thin structure like behavior pattern.

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Figure 4. Behavior pattern map for MOS tunnel diodes with [9] A. Faigon, F. Campabadal. Solid St. Electron. 39, 2, n-type substrate. The boundaries between regions were calculated (1996).

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